1. Field of the Invention
The present invention relates to a method for fabricating a non-volatile memory cell, and more particularly to a method for fabricating a flash memory cell.
2. Description of the Prior Art
With enlargement of an application field such as a portable telephone and digital still camera, an EEPROM (Electrically Erasable and Programmable Read Only Memory) has rapidly come into wide use. The EEPROM, which permits electrical simultaneous erase of data, is called a flash EEPROM.
The EEPROM is a non-volatile semiconductor memory device which stores digital information with two or more values according to whether or not a prescribed quantity of charges is stored and reads the digital information by a change in the conduction of a channel region corresponding to the quantity of charges.
For the conventional flash EEPROM device, each memory cell is based on a MOS transistor element (called a floating-gate transistor) composed of a tunnel oxide layer, a floating gate, a gate dielectric layer with an oxide/nitride/oxide (ONO) structure, a control gate, a source region and a drain region. The floating gate is so named due to the fact that it is physically but not electrically isolated from all the other conductive elements in the flash EEPROM device. The floating gate is located beneath the control gate and isolated by the gate dielectric layer from the control gate. The control gate is electrically connected to one word line of the flash EEPROM device.
However, in the conventional method for fabricating a flash EEPROM cell, after the ONO gate dielectric layer is deposited, a first polysilicon layer and the tunnel oxide layer on the periphery region are removed by patterning the ONO gate dielectric layer with a photolithography and etching method. Then, a gate oxide layer and a second polysilicon layer are formed on the periphery region and on the ONO gate dielectric layer of a memory cell region. As a consequence, the ONO gate dielectric layer is exposed in various solvents and gases. For example, the ONO gate dielectric layer would be exposed in an acidic solution for stripping a photoresist, a purified purge gas/or a purified solvent used in surface clean process and H2O/or oxygen gas used in a thermal oxidation for the formation of the gate oxide layer of the periphery region. Thus, many adverse effects are caused on the ONO gate dielectric layer.
Moreover, in order to prevent the loss of the ONO gate dielectric layer, the surface clean process prior to the formation of the gate oxide layer of the periphery region is significantly limited. Hence, the gate oxide layer of the periphery region is also disadvantageously influenced.
Accordingly, it is an intention to provide a method for fabricating a flash memory cell with a high-quality gate dielectric layer, which can overcome the above drawbacks.